Many synchronous semiconductor memories, such as dynamic random access memory (“DRAM”), operate using an input supply voltage and input system clock signal. When the system clock enters into the memory, the clock signal is typically delayed by the internal components of the memory. In order to compensate for the inherent delay in the memory, the memory must synchronize the internal, delayed clock signal with the system clock. Memories typically employ a clock circuit such as a delay locked loop (“DLL”) or a phase locked loop (“PLL”). The clock circuit adjusts the timing of internal clock relative to the external clock to account for the internal delay of the memory and ensures that the internal dock of the memory has a timing relative to the external clock so that memory operations, such providing data, receiving data, and receiving commands and address information, is in phase with the external clock of the system. Additionally, typical memories also include a duty cycle correction circuit (“DCC”) for generating an internal clock signal with a duty cycle of approximately 50%.
In ideal systems, where the external clock signal and the supply voltage are constant in time, a phase detector in the DLL compares the internal clock phase with the external clock phase in order to determine the proper phase delay to apply in providing the internal clock. In the ideal situation, the DLL could discontinue comparing the internal and external clock cycles once a lock is achieved and continue to apply the determined delay in order to lock the internal and external docks. The process of comparison and determining the necessary delay is typically known as “tracking.” However, external clocks are not ideal clocks because the frequency and duty cycle of the external clock are subject to change over time. Moreover, the magnitude of the supply voltage may also vary over time, causing circuit performance of circuits in the memory to vary as well. The result of these variations is that a determined delay which achieved a lock at one point in time may be insufficient or excessive to achieve a lock at a later point in time.
One way to compensate for the variations in the external clock is to leave DLL tracking on at all times. This method ensures that the internal and external clocks are always locked but is costly in terms of power consumption. Another approach would be to periodically enable DLL tracking based on the activity of the device. For example, DLL tracking may be enabled only when a read event occurs in the device. Periodic DLL tracking represents a lower power alternative to tracking all of the time, but this type of tracking is largely speculative and may enable DLL tracking when no tracking is needed or may fail to enable tracking even when the external clock or system power supply is particularly volatile.